This invention relates to multiplier-accumulator devices performing the algebraic sum of products of operands and more particularly, to devices of the type processing operands expressed in true form and in two's complement form. In particular, these devices can be used in data or signal processing systems.
In digital signal processing systems, various algebraic operations may be carried out on the signals, in real time, during processing. Consequently, in order not to disturb the processing operation, it is necessary that the results of these operations be obtained as quickly as possible. One of the operations which is often carried out is the accumulation of products of two numbers. An example is the digital filtering function which involves an accumulation of products to obtain the value of each sample of the filtered signal. In effect, each sample Y.sub.i of the filtered signal is equal to ##EQU1## WHERE X.sub.i-k represents the samples of the signal to be filtered and
C.sub.k the filter coefficients.
In order to have Y.sub.i correctly calculated, it is necessary that the multiplying and accumulating operations involving any sample X.sub.i-k, be terminated before the arrival of the next sample at the filter input.
There are multiplying-accumulating devices including two particular assemblies, the first one carrying out the multiplications, and the second one carrying out the accumulations. To reduce the time required to obtain the final result, it is possible to increase the speed of each assembly. However, this speed cannot indefinitely be increased and consequently, it is desirable to provide other means to increase the overall speed of the multiplier-accumulators.
An algorithm generally in use to carry out a binary multiplication of two n-bit operands consists in accumulating a series of partial products into a 2n position accumulator. Each partial product is obtained by multiplying the multiplicand by a bit of the multiplier. The low order bit of the multiplier controls the generation of the first partial product. Before adding a new partial product, the sum of the previous partial products is shifted to the right one bit position in the accumulator.
In these multipliers, the first partial product is accumulated into the first n left-hand positions of the accumulator. Due to the shift to the right performed before accumulating the successive partial products, at the end of the multiplying operation, the accumulator contains the final product, with the bit of lowest weight in the right-hand position.
If a second product of two operands is to be added, it is impossible to use the same accumulator since the bits with the same weight of the second set of partial products and of the first product would not be added. Then, it is necessary to provide a second accumulator in which the products are added.
In addition, in these devices, the multiplication does not take the operand sign into account. The signs are separately processed which involves additional circuits and extra time to correct the product sign at the end of each multiplying operation.
Therefore, an object of this invention, is to provide a fast multiplier-accumulator device using the principle of multiplication by successive additions.
Another object of this invention is to provide such a device using a minimum of circuits.
Another object of this invention is to provide such a device able to process positive or negative operands expressed in true form or in two's complement code.